Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

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Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
209
2.4.3.7
Port C Data Direction Register (DDRC)
2.4.3.8
Port D Data Direction Register (DDRD)
 Address 0x0006 (
)
Access: User read/write
1
1
Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
 R
DDRC7
DDRC6
DDRC5
DDRA4
DDRC3
DDRC2
DDRC1
DDRC0
 W
Reset
0
0
0
0
0
0
0
0
 Address 0x0006 (
,
)
Access: User read only
7
6
5
4
3
2
1
0
 
R
0
0
0
0
0
0
0
0
 W
Reset
0
0
0
0
0
0
0
0
Figure 2-8. Port C Data Direction Register (DDRC)
Table 2-28. DDRC Register Field Descriptions
Field
Description
7-0
DDRC
Port C Data Direction
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
 Address 0x0007 (
)
Access: User read/write
1
1
Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
 R
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
 W
Reset
0
0
0
0
0
0
0
0
 Address 0x0007 (
,
)
Access: User read only
7
6
5
4
3
2
1
0
 
R
0
0
0
0
0
0
0
0
 W
Reset
0
0
0
0
0
0
0
0
Figure 2-9. Port D Data Direction Register (DDRD)