Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
216
Freescale Semiconductor
2.4.3.17
Port T Data Direction Register (DDRT)
Table 2-36. PTIT Register Field Descriptions
Field
Description
7-0
PTIT
Port T input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0242 (
,
)
Access: User read/write
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
W
Reset
0
0
0
0
0
0
0
0
Address 0x0242 (
)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-18. Port T Data Direction Register (DDRT)
Table 2-37. DDRT Register Field Descriptions
Field
Description
7-0
DDRT
Port T data direction—
This bit determines whether the pin is a general-purpose input or output.
This bit determines whether the pin is a general-purpose input or output.
1 Associated pin configured as output
0 Associated pin configured as input
0 Associated pin configured as input