Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

Freescale Semiconductor

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This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.

The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.

The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:

•

•

External instruction tagging feature is part of the DBG module

•

S12SBDM register map and register content modified

•

Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)

•

Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)

The BDM includes these distinctive features:

•

Single-wire communication with host development system

•

Enhanced capability for allowing more flexibility in clock rates

•

1.03

14.May.2009

Internal Conditional text only

1.04

30.Nov.2009

Internal Conditional text only

1.05

07.Dec.2010

Standardized format of revision history table header.

1.06

02.Mar.2011

Corrected BPAE bit description.
Removed references to fixed VCO frequencies