Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

320

Freescale Semiconductor

Read: Anytime

Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.

Read: Anytime

Write: Anytime the module is disarmed.

This register configures the comparators for range matching.

6

TSOURCE

Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU
system is secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested

3–2

TRCMOD

Trace Mode Bits — See

for detailed Trace Mode descriptions. In Normal Mode,

change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries
into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored.
In Compressed Pure PC mode the program counter value for each instruction executed is stored. See

.

0

TALIGN

Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data

00

Normal

01

Loop1

10

Detail

11

Compressed Pure PC

Address: 0x0023

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

ABCM

W

Reset

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

1–0

ABCM[1:0]

A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in