Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
326
Freescale Semiconductor
The priorities described in
dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2).
8.3.2.7.4
Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further comparator matches on the same channel in the same session have no affect on that flag.
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further comparator matches on the same channel in the same session have no affect on that flag.
8.3.2.8
Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module
register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data
bus compare registers, two data bus mask registers and a control register). Comparator B consists of four
register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data
bus compare registers, two data bus mask registers and a control register). Comparator B consists of four
0001
Match2 to State2........ Match1 to Final State
0010
Match0 to Final State....... Match1 to State1
0011
Match1 to Final State....... Match2 to State1
0100
Match1 to State2
0101
Match1 to Final State
0110
Match2 to State2........ Match0 to Final State
0111
Match0 to Final State
1000
Reserved
1001
Reserved
1010
Either Match1 or Match2 to State1....... Match0 to Final State
1011
Reserved
1100
Reserved
1101
Either Match1 or Match2 to Final State....... Match0 to State1
1110
Match0 to State2....... Match2 to Final State
1111
Reserved
Address: 0x0027
7
6
5
4
3
2
1
0
R
0
0
0
0
0
MC2
MC1
MC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-12. Debug Match Flag Register (DBGMFR)
Table 8-20. State3 — Sequencer Next State Selection
SC[3:0]
Description (Unspecified matches have no effect)