Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

Модели

TWR-S12GN32-KIT

S12 Clock, Reset and Power Management Unit (S12CPMU)

MC9S12G Family Reference Manual,

Rev.1.23

382

Freescale Semiconductor

10.3.2.8

S12CPMU RTI Control Register (CPMURTI)

This register selects the time-out period for the Real Time Interrupt.

The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.

Read: Anytime

Write: Anytime

NOTE

A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.

0x003B

RTDEC

RTR6

RTR5

RTR4

RTR3

RTR2

RTR1

RTR0

Reset

Figure 10-11. S12CPMU RTI Control Register (CPMURTI)

Table 10-9. CPMURTI Field Descriptions

Field

Description

RTDEC

Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See

Table 10-10

1 Decimal based divider value. See

Table 10-11

6–4

RTR[6:4]

Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See

Table 10-10

and

Table 10-11

3–0

RTR[3:0]

Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.