Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

Freescale Semiconductor

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S12 CPU is a high-speed 16-bit processing unit:

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Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution

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Includes many single-byte instructions. This allows much more efficient use of ROM space.

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Extensive set of indexed addressing capabilities, including:

— Using the stack pointer as an indexing register in all indexed operations

— Using the program counter as an indexing register in all but auto increment/decrement mode

— Accumulator offsets using A, B, or D accumulators

— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)

On-chip flash memory on the MC9S12G-Family family features the following:

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Up to 240 Kbyte of program flash memory

— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection

— Erase sector size 512 bytes

— Automated program and erase algorithm

— User margin level setting for reads

— Protection scheme to prevent accidental program or erase

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Up to 4 Kbyte EEPROM

— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection

— Erase sector size 4 bytes

— Automated program and erase algorithm

— User margin level setting for reads

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Up to 11 Kbytes of general-purpose RAM

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Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used
as general-purpose I/O

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Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J
and AD on per-pin basis

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Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis
and on BKGD pin

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Control registers to enable/disable open-drain (wired-or) mode on ports S and M