Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

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Freescale Semiconductor

Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.

The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage
level. The POR is deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage
levels are not specified in this document because this internal supply is not visible on device pins).

The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDF or VDDX drops below
an appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum
speed. The LVR assert and deassert levels for the supply voltage VDDX are V

LVRXA

and V

LVRXD

and are

specified in the device Reference Manual.

The interrupt/reset vectors requested by the S12CPMU are listed in

. Refer to MCU

specification for related vector addresses and priorities.

The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to
run, else the RTI counter halts in Stop Mode.

RTI time-out interrupt

I bit

CPMUINT (RTIE)

PLL lock interrupt

I bit

CPMUINT (LOCKIE)

Oscillator status

interrupt

I bit

CPMUINT (OSCIE)

Low voltage interrupt

I bit

CPMULVCTL (LVIE)

Autonomous

Periodical Interrupt

I bit

CPMUAPICTL (APIE)