Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Analog-to-Digital Converter (ADC12B8CV2)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
451
12.3.2.3
ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Table 12-5. External Trigger Channel Select Coding
ETRIGSEL
ETRIGCH3
ETRIGCH2
ETRIGCH1
ETRIGCH0
External trigger source is
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN7
0
1
0
0
1
AN7
0
1
0
1
0
AN7
0
1
0
1
1
AN7
0
1
1
0
0
AN7
0
1
1
0
1
AN7
0
1
1
1
0
AN7
0
1
1
1
1
AN7
1
0
0
0
0
ETRIG0
1
1
Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
1
0
0
0
1
ETRIG1
1
1
0
0
1
0
ETRIG2
1
1
0
0
1
1
ETRIG3
1
1
0
1
X
X
Reserved
1
1
X
X
X
Reserved
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
0
AFFC
Reserved
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACMPIE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-5. ATD Control Register 2 (ATDCTL2)