Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

Модели

TWR-S12GN32-KIT

Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor

617

18.3.3.5

Time Stamp Register (TSRH–TSRL)

If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see

Section 18.3.2.1,

“MSCAN Control Register 0 (CANCTL0)

”). In case of a transmission, the CPU can only read the time

stamp after the respective transmit buffer has been flagged empty.

The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.

Module Base + 0x00XD

Access: User read/write

Read: Anytime when TXEx flag is set (see

Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)

”) and the

corresponding transmit buffer is selected in CANTBSEL (see

Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)

”)

Write: Anytime when TXEx flag is set (see

Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)

”) and the