Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

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Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
639
19.3
Memory Map and Register Definition
19.3.1
Module Memory Map
This section describes the content of the registers in the scalable PWM module. The base address of the
scalable PWM module is determined at the MCU level when the MCU is defined. The register decode map
is fixed and begins at the first address of the module address offset. The figure below shows the registers
associated with the scalable PWM and their relative offset from the base address. The register detail
description follows the order they appear in the register map.
Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented
functions are indicated by shading the bit.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
19.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the scalable PWM module.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
PWME
1
R
PWME7
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
W
0x0001
R
PPOL7
PPOL6
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
W
0x0002
R
PCLK7
PCLKL6
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
W
0x0003
PWMPRCLK
R
0
PCKB2
PCKB1
PCKB0
0
PCKA2
PCKA1
PCKA0
W
0x0004
PWMCAE
R
CAE7
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
W
0x0005
PWMCTL
R
CON67
CON45
CON23
CON01
PSWAI
PFRZ
0
0
W
0x0006
PWMCLKAB
R
PCLKAB7
PCLKAB6
PCLKAB5
PCLKAB4
PCLKAB3
PCLKAB2
PCLKAB1
PCLKAB0
W
= Unimplemented or Reserved
Figure 19-2. The scalable PWM Register Summary (Sheet 1 of 4)