Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

652

Freescale Semiconductor

•

The counter is written (counter resets to $00)

•

The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.

Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.

See

 for more information.

To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:

•

Left aligned output (CAEx = 0)

PWMx Period = Channel Clock Period * PWMPERx

•

Center Aligned Output (CAEx = 1)

PWMx Period = Channel Clock Period * (2 * PWMPERx)

For boundary case programming values, please refer to

.

1

This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.

Read: Anytime

Write: Anytime

There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.

The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:

•

The effective period ends

•

The counter is written (counter resets to $00)

Module Base + 0x0014 = PWMPER0, 0x0015 = PWMPER1, 0x0016 = PWMPER2, 0x0017 = PWMPER3
Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7

7

6

5

4

3

2

1

0

R

Bit 7

 6

 5

 4

 3

 2

 1

 Bit 0

W

Reset

1

1

1

1

1

1

1

1