Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Serial Communication Interface (S12SCIV5)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
701
If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
20.5.2.3
Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not
affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from
where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset
aborts any transmission or reception in progress and resets the SCI.
affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from
where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset
aborts any transmission or reception in progress and resets the SCI.
The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input
can be used to bring the CPU out of stop mode.
can be used to bring the CPU out of stop mode.
20.5.3
Interrupt Operation
This section describes the interrupt originated by the SCI block.The MCU must service the interrupt
requests.
requests.
20.5.3.1
Description of Interrupt Operation
The SCI only originates interrupt requests. The following is a description of how the SCI makes a request
and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are
chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and
all the following interrupts, when generated, are ORed together and issued through that port.
and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are
chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and
all the following interrupts, when generated, are ORed together and issued through that port.
20.5.3.1.1
TDRE Description
The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI
data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a
data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a
Table 20-20. SCI Interrupt Sources
Interrupt
Source
Local Enable
Description
TDRE
SCISR1[7]
TIE
Active high level. Indicates that a byte was transferred from SCIDRH/L to the
transmit shift register.
transmit shift register.
TC
SCISR1[6]
TCIE
Active high level. Indicates that a transmit is complete.
RDRF
SCISR1[5]
RIE
Active high level. The RDRF interrupt indicates that received data is available
in the SCI data register.
in the SCI data register.
OR
SCISR1[3]
Active high level. This interrupt indicates that an overrun condition has occurred.
IDLE
SCISR1[4]
ILIE
Active high level. Indicates that receiver input has become idle.
RXEDGIF
SCIASR1[7]
RXEDGIE
Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for
RXPOL = 1) was detected.
RXPOL = 1) was detected.
BERRIF
SCIASR1[1]
BERRIE
Active high level. Indicates that a mismatch between transmitted and received data
in a single wire application has happened.
in a single wire application has happened.
BKDIF
SCIASR1[0]
BRKDIE
Active high level. Indicates that a break character has been received.