Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

750

Freescale Semiconductor

Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a
glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.

The reset state of each individual bit is listed within

which details the registers and their bit fields

This section describes interrupts originated by the TIM16B6CV3 block.

 lists the interrupts

generated by the TIM16B6CV3 to communicate with the MCU.

The TIM16B6CV3 could use up to 7 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.

This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt. The TIM
block only generates the interrupt and does not service it. Only bits related to implemented channels are
valid.

This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block
only generates the interrupt and does not service it.

TIM16B6CV3

C[5:0]F

—

—

—

Timer Channel 5–0

Active high timer channel interrupts 5–0

TOF

—

—

—

Timer Overflow

Timer Overflow interrupt