Техническая Спецификация для Atmel Evaluation Board using the SAM7SE Microcontroller AT91SAM7SE-EK AT91SAM7SE-EK
Модели
AT91SAM7SE-EK
16
6295A–ATARM–27-Mar-07
Application Note
3.2.7
Using the Debug Unit
3.2.7.1
Purpose
The Debug Unit provides a two-pins Universal Asynchronous Receiver and Transmitter (UART)
as well as several other debug functionalities. The UART is ideal for outputting debug traces on
a terminal, or as an In-System Programming (ISP) communication port. Other features include
chip identification registers, management of debug signals from the ARM core, and so on.
as well as several other debug functionalities. The UART is ideal for outputting debug traces on
a terminal, or as an In-System Programming (ISP) communication port. Other features include
chip identification registers, management of debug signals from the ARM core, and so on.
The DBGU is used in the example to output a single string of text whenever the application
starts. It is configured with a baudrate of 115200, 8 bits of data, no parity, one stop bit and no
flow control.
starts. It is configured with a baudrate of 115200, 8 bits of data, no parity, one stop bit and no
flow control.
3.2.7.2
Initialization
As the Debug Unit is part of the System Controller peripheral, there is no need to enable its clock
in the PMC. The DBGU is continuously clocked and cannot be disabled. However, it is neces-
sary to configure its two pins (DTXD and DRXD) in the PIO controller.
in the PMC. The DBGU is continuously clocked and cannot be disabled. However, it is neces-
sary to configure its two pins (DTXD and DRXD) in the PIO controller.
Writing both pin IDs in the PIO Disable Register (PDR) of the corresponding PIO controller
enables peripheral control on those pins. However, some PIOs are shared between two different
peripherals; Peripheral A Select Register (ASR) and Peripheral B Selected Register (BSR) are
used to switch control between the two.
enables peripheral control on those pins. However, some PIOs are shared between two different
peripherals; Peripheral A Select Register (ASR) and Peripheral B Selected Register (BSR) are
used to switch control between the two.
The very next action to perform is to disable the receiver and transmitter logic, as well as disable
interrupts. This enables smooth reconfiguration of the peripheral in case it had already been ini-
tialized during a previous execution of the application. Setting bits RSTRX and RSTTX in the
Control Register (CR) of the DBGU resets and disables the received and transmitter, respec-
tively. Setting all bits of the Interrupt Disable Register (IDR) disable all interrupts coming from the
Debug Unit.
interrupts. This enables smooth reconfiguration of the peripheral in case it had already been ini-
tialized during a previous execution of the application. Setting bits RSTRX and RSTTX in the
Control Register (CR) of the DBGU resets and disables the received and transmitter, respec-
tively. Setting all bits of the Interrupt Disable Register (IDR) disable all interrupts coming from the
Debug Unit.
The baud rate clock must now be set up. The input clock is equal to MCK divided by a program-
mable factor. The Clock Divisor value is held in the Baud Rate Generate Register (BRGR). The
following values are possible:
mable factor. The Clock Divisor value is held in the Baud Rate Generate Register (BRGR). The
following values are possible:
The following formula can be used to compute the value of CD given the microcontroller operat-
ing frequency and the desired baud rate:
ing frequency and the desired baud rate:
For example, a 115200 baud rate can be obtained with a 48MHz master clock frequency by writ-
ing a value of 26 in CD. Obviously, there is a slight deviation from the desired baudrate; these
values yield a true rate of 115384 bauds. However, it is a mere 1.6% error, so it does not have
any impact in practice.
ing a value of 26 in CD. Obviously, there is a slight deviation from the desired baudrate; these
values yield a true rate of 115384 bauds. However, it is a mere 1.6% error, so it does not have
any impact in practice.
The Mode Register (MR) has two configurable values. The first one is the Channel Mode in
which the DBGU is operating. Several modes are available for testing purpose; in this example,
which the DBGU is operating. Several modes are available for testing purpose; in this example,
Table 3-1.
Possible Values for the Clock Divisor field of BRGR
Value
Comment
0
Baud rate clock is disabled
1
Baud rate clock is MCK divided by 16
2 to 65535
Baud rate clock is MCK divided by (CD x 16)
CD
MCK
16
Baudrate
×
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