Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK
Модели
AT91SAM9M10-G45-EK
22
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
z
memory to memory transfer
z
Peripheral to memory
z
Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are also given below in
peripherals below. The hardware interface numbers are also given below in
6.6
Debug and Test Features
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ARM926 Real-time In-circuit Emulator
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Two real-time Watchpoint Units
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Two Independent Registers: Debug Control Register and Debug Status Register
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Test Access Port Accessible through JTAG Protocol
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Debug Communications Channel
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Debug Unit
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Two-pin UART
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Debug Communication Channel Interrupt Handling
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Chip ID Register
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IEEE1149.1 JTAG Boundary-scan on All Digital Pins.
Table 6-7.
DMA Channel Definition
Instance Name
T/R
DMA Channel HW
interface Number
interface Number
MCI0
TX/RX
0
SPI0 TX
1
SPI0
RX
2
SPI1
TX
3
SPI1
RX
4
SSC0
TX
5
SSC0 RX
6
SSC1
TX
7
SSC1
RX
8
AC97C
TX
9
AC97C
RX
10
MCI1
TX/RX
13