Техническая Спецификация для Atmel MCU Evaluation Kit AT91SAM7X-EK AT91SAM7X-EK

 2

SAM7X Series [SUMMARY DATASHEET]

6120IS–ATARM–14-Nov-13

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Incorporates the ARM7TDMI ARM Thumb

®

 Processor

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High-performance 32-bit RISC Architecture

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High-density 16-bit Instruction Set

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Leader in MIPS/Watt

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EmbeddedICE

™

 In-circuit Emulation, Debug Communication Channel Support

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Internal High-speed Flash 

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512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of
256 Bytes (Dual Plane)

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256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane)

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128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane)

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Single Cycle Access at Up to 30 MHz in Worst Case Conditions

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Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

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Page Programming Time: 6 ms, Including Page Auto-erase,
Full Erase Time: 15 ms

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10,000 Write Cycles, 10-year Data Retention Capability,
Sector Lock Capabilities, Flash Security Bit

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Fast Flash Programming Interface for High Volume Production

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Internal High-speed SRAM, Single-cycle Access at Maximum Speed

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128 Kbytes (SAM7X512)

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64 Kbytes (SAM7X256)

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32 Kbytes (SAM7X128)

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Memory Controller (MC)

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Embedded Flash Controller, Abort Status and Misalignment Detection

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Reset Controller (RSTC)

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Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector

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Provides External Reset Signal Shaping and Reset Source Status

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Clock Generator (CKGR)

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Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

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Power Management Controller (PMC)

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Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode

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Four Programmable External Clock Signals

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Advanced Interrupt Controller (AIC)

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Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

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Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected

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Debug Unit (DBGU)

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2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention

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Mode for General Purpose 2-wire UART Serial Communication

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Periodic Interval Timer (PIT)

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20-bit Programmable Counter plus 12-bit Interval Counter

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Windowed Watchdog (WDT)

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12-bit key-protected Programmable Counter

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Provides Reset or Interrupt Signals to the System

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Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

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Real-time Timer (RTT)

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32-bit Free-running Counter with Alarm

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Runs Off the Internal RC Oscillator

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Two Parallel Input/Output Controllers (PIO) 

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Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os 

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Input Change Interrupt Capability on Each I/O Line