Техническая Спецификация для Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK
Модели
AT91SAM9N12-EK
Glossary
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
Glossary-3
Architecture
The organization of hardware and/or software that characterizes a processor and its
attached components, and enables devices with similar characteristics to be grouped
together when describing their behavior, for example, Harvard architecture, instruction
set architecture, ARMv6 architecture.
attached components, and enables devices with similar characteristics to be grouped
together when describing their behavior, for example, Harvard architecture, instruction
set architecture, ARMv6 architecture.
ARM instruction
Is a word that specifies an operation for an ARM processor to perform. ARM
instructions must be word-aligned.
instructions must be word-aligned.
ARM state
A processor that is executing ARM (32-bit) word-aligned instructions is operating in
ARM state.
ARM state.
ASIC
See Application Specific Integrated Circuit.
ASSP
See Application Specific Standard Part/Product.
ATPG
See Automatic Test Pattern Generation.
Automatic Test Pattern Generation (ATPG)
The process of automatically generating manufacturing test vectors for an ASIC design,
using a specialized software tool.
using a specialized software tool.
Back-annotation
The process of applying timing characteristics from the implementation process onto a
model.
model.
Banked registers
Those physical registers whose use is defined by the current processor mode. The
banked registers are r8 to r14.
banked registers are r8 to r14.
Base register
A register specified by a load or store instruction that is used to hold the base value for
the instruction’s address calculation. Depending on the instruction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the
virtual address which is sent to memory.
the instruction’s address calculation. Depending on the instruction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the
virtual address which is sent to memory.
Base register write-back
Updating the contents of the base register used in an instruction target address
calculation so that the modified address is changed to the next higher or lower
sequential address in memory. This means that it is not necessary to fetch the target
address for successive instruction transfers and enables faster burst accesses to
sequential memory.
calculation so that the modified address is changed to the next higher or lower
sequential address in memory. This means that it is not necessary to fetch the target
address for successive instruction transfers and enables faster burst accesses to
sequential memory.
Beat
Alternative word for an individual transfer within a burst. For example, an INCR4 burst
comprises four beats.
comprises four beats.
See also Burst.
Big-endian
Byte ordering scheme in which bytes of decreasing significance in a data word are
stored at increasing addresses in memory.
stored at increasing addresses in memory.
See also Little-endian and Endianness.