Техническая Спецификация для Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

For information on the Static Memory Controller, refer to the Static Memory Controller section of this datazsheet.

The product embeds a multi-port DDR2SDR Controller. This allows to use three additional ports on DDR2SDRC to
lessen the EBI load from a part of DDR2 or LP-DDR accesses. This increases the bandwidth when DDR2 and NAND
Flash devices are used. This feature is NOT compatible with SDR or LP-SDR Memory.

It is controlled by DDR_MP_EN bit in EBI Chip Select Assignment Register.

For information on the PMECC Controller, refer to PMECC and PMERRLOC sections; also refer to Boot Strategies
Section, NAND Flash Boot: PMECC Error Detection and Correction.

External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices.

The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the
EBI_CSA field in the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables the
NAND Flash logic.

 

For details on this register, refer to the Bus Matrix Section. Access to an external NAND Flash device

is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).

The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals
when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the
NCS3 address space. See 

 for more information. For details on these waveforms, refer to the

Static Memory Controller section.

Bus Matrix

DDR2SDRC

Port 2

Port 1

Port 0

EBI

DDR2 or LP-DDR

Device

NAND Flash

Device

Port 3

Bus Matrix

DDR2SDRC

not used

not used

Port 0

EBI

(LP-)SDR

Device

NAND Flash

Device

not used