Техническая Спецификация для Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK
Модели
AT91SAM9G25-EK
712
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
37.8.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave
address devices.
address devices.
37.8.6.1 7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write)
accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When
performing read operations with an internal address, the TWI performs a write operation to set the internal address into
the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR)
is sometimes called “repeated start” (Sr) in I
accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When
performing read operations with an internal address, the TWI performs a write operation to set the internal address into
the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR)
is sometimes called “repeated start” (Sr) in I
2
C fully-compatible devices. See
for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0.
In the figures below the following abbreviations are used:
Figure 37-12.Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 37-13.Master Read with One, Two or Three Bytes Internal Address and One Data Byte
z
S
Start
z
Sr
Repeated Start
z
P
Stop
z
W
Write
z
R
Read
z
A
Acknowledge
z
N
Not Acknowledge
z
DADR
Device Address
z
IADR
Internal Address
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
DATA
A
P
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
P
DATA
A
A
IADR(7:0)
A
P
DATA
A
S
DADR
W
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
A
IADR(7:0)
A
S
DADR
W
DATA
N
P
Sr
DADR
R
A
Sr
DADR
R
A
DATA
N
P
Sr
DADR
R
A
DATA
N
P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address