Техническая Спецификация для Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK
Модели
AT91SAM9G25-EK
793
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
Figure 39-23.Timeguard Operations
indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function
of the Baud Rate.
39.7.3.11 Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the
RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can
generate an interrupt, thus indicating to the driver an end of frame.
RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can
generate an interrupt, thus indicating to the driver an end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no
time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit counter with the
value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.
Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no
time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit counter with the
value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.
Then, the user can either:
z
Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR)
with the STTTO (Start Time-out) bit to 1. In this case, the idle state on RXD before a new character is received will
not provide a time-out. This prevents having to handle an interrupt before a character is received and allows
waiting for the next idle state on RXD after a frame is received.
with the STTTO (Start Time-out) bit to 1. In this case, the idle state on RXD before a new character is received will
not provide a time-out. This prevents having to handle an interrupt before a character is received and allows
waiting for the next idle state on RXD after a frame is received.
z
Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and
Start Time-out) bit to 1. If RETTO is performed, the counter starts counting down immediately from the value TO.
Start Time-out) bit to 1. If RETTO is performed, the counter starts counting down immediately from the value TO.
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Start
Bit
TG = 4
Write
US_THR
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
TXRDY
TXEMPTY
TG = 4
Table 39-10. Maximum Timeguard Length Depending on Baud Rate
Baud Rate
Bit time
Timeguard
Bit/sec
µs
ms
1 200
833
212.50
9 600
104
26.56
14400 69.4
17.71
19200
52.1
13.28
28800
34.7
8.85
33400
29.9
7.63
56000
17.9
4.55
57600
17.4
4.43
115200
8.7
2.21