Техническая Спецификация для Atmel SAM4S Xplained Pro Starter and Evaluation Kit ATSAM4S-XPRO ATSAM4S-XPRO
Модели
ATSAM4S-XPRO
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
276
14.4
Functional Description
14.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and
generates the following reset signals:
proc_nreset: processor reset line. It also resets the Watchdog Timer.
periph_nreset: affects the whole set of embedded peripherals
nrst_out: drives the NRST pin
These reset signals are asserted by the Reset Controller, either on external events or on software action. The
Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an
assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device
resets.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered
with VDDIO, so that its configuration is saved as long as VDDIO is on.
14.4.2 NRST Manager
After power-up, NRST is an output during the ERSTL time period defined in the RSTC_MR. When ERSTL has
elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external
signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State
Manager.
Figure 14-2.
NRST Manager
14.4.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is
reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs.
Writing a 0 to bit URSTEN in the RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in bit NRSTL (NRST level) in the RSTC_SR. As soon as the pin
The level of the pin NRST can be read at any time in bit NRSTL (NRST level) in the RSTC_SR. As soon as the pin
NRST is asserted, bit URSTS in the RSTC_SR is set. This bit clears only when the RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, a 1
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, a 1
must be written to bit URSTIEN in the RSTC_MR.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset