Техническая Спецификация для Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK
Модели
AT91SAM9N12-EK
890
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
42.8.5 ADC
Channel
Enable Register
Name:
ADC_CHER
Address:
0xF804C010
Access:
Write-only
This register can only be written if the WPEN bit is cleared in
.
• CHx: Channel x Enable
0: No effect.
1: Enables the corresponding channel.
Note:
If USEQ = 1 in the ADC_MR register, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1
and ADC_SEQR2.
and ADC_SEQR2.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
CH11
CH10
CH9
CH8
7
6
5
4
3
2
1
0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0