Техническая Спецификация для Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK

1095

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

Note:

1. For DDR2 usage only, there are no limitations to LP-DDR, SDRAM and mobile SDRAM.

The master clock is the maximum clock at which the system is able to run. It is given by the smallest value of the internal 
bus clock and EBI clock.

Note:

1. For DDR2 usage only, there are no limitations to LP-DDR, SDRAM and mobile SDRAM.

Note:

1. The C

CRYSTAL

 value is specified by the crystal manufacturer. In our case, C

CRYSTAL

 must be between 15 pF and 20 pF. 

All parasitic capacitance, package and board, must be calculated in order to reach 15 pF (minimum targeted load for 
the oscillator) by taking into account the internal load C

INT

. So, to target the minimum oscillator load of 15 pF, external 

capacitance must be: 15 pF - 4 pF = 11 pF which means that 22 pF is the target value (22 pF from XIN to GND and 
22 pF from XOUT to GND). If 20 pF load is targeted, the sum of pad, package, board and external capacitances must 
be 20 pF - 4 pF = 16 pF which means 32 pF (32 pF from XIN to GND and 32 pF from XOUT to GND).

1/(t

CPPCK

)

Processor Clock Frequency

V

DDCORE

 = 0.9V, T

A

 = 85°C

125

400

MHz

1/(t

CPMCK

)

Master Clock Frequency

V

DDCORE

 = 0.9V, T

A

 = 85°C

125

133

MHz

1/(t

CPMAIN

)

Crystal Oscillator Frequency

12

16

MHz

C

CRYSTAL

Crystal Load Capacitance

15

20

pF

C

LEXT

External Load Capacitance

C

CRYSTAL

 = 15 pF

27

pF

C

CRYSTAL

 = 20 pF

32

pF

Duty Cycle

40

60

%

t

ST

Startup Time

2

ms

I

DDST

Standby Current Consumption

Standby mode

1

µ

A

P

ON

Drive Level

150

µ

W

I

DD ON

Current Dissipation

@ 12 MHz

0.52

0.55

mA

@ 16 MHz

0.7

1.1

mA