Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK

 159

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use
at the moment.

 details the connections between the two Memory Controllers and the EBI pins.

EBI I/O Lines Description 

EBI_D0 - EBI_D31

Data Bus

I/O

EBI_A0 - EBI_A25

Address Bus

Output

EBI_NWAIT

External Wait Signal

Input

Low

EBI_NCS0 - EBI_NCS5

Chip Select Lines

Output

Low

EBI_NWR0 - EBI_NWR3

Write Signals

Output

Low

EBI_NRD

Read Signal

Output

Low

EBI_NWE

Write Enable

Output

Low

EBI_NBS0 - EBI_NBS3

Byte Mask Signals

Output

Low

EBI_NANDCS

NAND Flash Chip Select Line

Output

Low

EBI_NANDOE

NAND Flash Output Enable

Output

Low

EBI_NANDWE

NAND Flash Write Enable

Output

Low

EBI_SDCK, EBI_SDCK#

DDR2/SDRAM Differential Clock

Output

EBI_SDCKE

DDR2/SDRAM Clock Enable

Output

High

EBI_SDCS

DDR2/SDRAM Controller Chip Select Line

Output

Low

EBI_BA0 - EBI_BA1

Bank Select

Output

EBI_SDWE

DDR2/SDRAM Write Enable

Output

Low

EBI_RAS - EBI_CAS

Row and Column Signal

Output

Low

EBI_SDA10

SDRAM Address 10 Line

Output

EBI Pins and Memory Controllers I/O Lines Connections

EBI_NWR1/NBS1/CFIOR

NBS1

NWR1

EBI_A0/NBS0

Not Supported

SMC_A0

EBI_A1/NBS2/NWR2

Not Supported

SMC_A1

EBI_A[11:2]

SDRAMC_A[9:0]

SMC_A[11:2]

EBI_SDA10

SDRAMC_A10

Not Supported

EBI_A12

Not Supported

SMC_A12

EBI_A[14:13]

SDRAMC_A[12:11]

SMC_A[14:13]

EBI_A[25:15]

Not Supported

SMC_A[25:15]

EBI_D[31:0]

D[31:0]

D[31:0]