Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK

Модели

AT91SAM9M10-G45-EK

260

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

22.8.6

DDRSDRC Timing Parameter 2 Register

Name:

DDRSDRC_TPR2

Address:

0xFFFFE614 (0), 0xFFFFE414 (1)

Access:

Read-write

Reset:

See

This register can only be written if the bit WPEN is cleared in

• TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.

The Reset Value is 2 cycles.

This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.

Note: This field is found only in DDR2-SDRAM devices

• TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.

The Reset Value is 6 cycles.

This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.

Note: This field is found only in DDR2-SDRAM devices

• TRPA: Row Precharge All Delay

The Reset Value is 0 cycle.

This field defines the delay between a Precharge ALL banks Command and another command in number of cycles. Num-
ber of cycles is between 0 and 15.

Note: This field is found only in DDR2-SDRAM devices

• TRTP: Read to Precharge

The Reset Value is 2 cycles.

This field defines the delay between Read Command and a Precharge command in number of cycle.

Number of cycles is between 0 and 7.

–

TRTP

TRPA

TXARDS

TXARD