Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK

 61

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The SPI Flash bootloader tries to boot on SPI0 Chip Select 0, first looking for SPI Serial flash, and then for SPI
DataFlash.

It uses only one valid code detection: analysis of ARM exception vectors.

The SPI Flash read is done thanks to a Continuous Read command from address 0x0. This command is 0xE8 for
DataFlash and 0x0B for Serial Flash devices.

The SPI Flash Boot program supports all Atmel DataFlash devices.

The SPI Flash Boot program supports all Serial Flash devices.

The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes the ARM excep-
tion vectors.

TWI EEPROM Boot supports all I

2

C-compatible TWI EEPROM memories using 7 bits device address 0x50.

The NVM drivers use several PIOs in peripheral mode to communicate with devices. Care must be taken when
these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and
electrical conflicts between output pins used by the NVM drivers and the connected devices may occur.

To assure correct functionality, it is recommended to plug in critical devices to other pins not used by NVM.

 contains a list of pins that are driven during the boot program execution. These pins are driven during

the boot sequence for a period of less than 1 second if no correct boot program is found.

Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot pro-
gram are set to their reset state.

DataFlash Device

AT45DB011

1 Mbit

264

512 

AT45DB021

2 Mbits

264

1024

AT45DB041

4 Mbits

264

2048 

AT45DB081

8 Mbits

264

4096

AT45DB161

16 Mbits

528

4096

AT45DB321

32 Mbits

528

8192 

AT45DB642

64 Mbits

1056

8192

PIO Driven during Boot Program Execution 

NAND

EBI CS3 SMC

NANDCS

PIOC14

EBI CS3 SMC

NAND ALE

A21

EBI CS3 SMC

NAND CLE

A22

EBI CS3 SMC

Cmd/Addr/Data 

D[16:0]