Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK
Модели
AT91SAM9M10-G45-EK
68
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
12.4
Functional Description
12.4.1
Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at
Slow Clock and generates the following reset signals:
Slow Clock and generates the following reset signals:
• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• backup_nreset: Affects all the peripherals powered by VDDBU.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The
Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an
assertion of the NRST pin is required.
Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an
assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device
resets.
resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator
startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product documentation.
startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product documentation.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered
with VDDBU, so that its configuration is saved as long as VDDBU is on.
with VDDBU, so that its configuration is saved as long as VDDBU is on.
12.4.2
NRST Manager
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Man-
ager.
ager.
Figure 12-2.
NRST Manager
12.4.2.1
NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is
reported to the Reset State Manager.
reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writ-
ing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
ing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin
NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset