Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The MACB has several clock domains:

•      System bus clock (AHB and APB): DMA and register blocks

•      Transmit clock: transmit block

•      Receive clock: receive and address checker block

The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and
2.5 MHZ at 10 Mbps).

  illustrates the different blocks of the EMAC module.

The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes
of operation such as full- or half-duplex. 

The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the
address checking block and DMA interface.

The transmit block takes data from the DMA interface, adds preamble and, if necessary, pad and FCS, and trans-
mits data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol. The start of
transmission is deferred if CRS (carrier sense) is active.

If COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried
after a random back off. CRS and COL have no effect in full duplex mode.

The DMA block connects to external memory through its AHB bus interface. It contains receive and transmit FIFOs
for buffering frame data. It loads the transmit FIFO and empties the receive FIFO using AHB bus master opera-
tions. Receive data is not sent to memory until the address checking logic has determined that the frame should be
copied. Receive or transmit frames are stored in one or more buffers. Receive buffers have a fixed length of 128
bytes. Transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame.
The DMA block manages the transmit and receive framebuffer queues. These queues can hold multiple frames.

Synchronization module in the EMAC requires that the bus clock (hclk) runs at the speed of the macb_tx/rx_clk at
least, which is 25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps.

Frame data is transferred to and from the EMAC through the DMA interface. All transfers are 32-bit words and may
be single accesses or bursts of 2, 3 or 4 words. Burst accesses do not cross sixteen-byte boundaries. Bursts of 4
words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data
at the beginning or the end of a buffer.

The DMA controller performs six types of operation on the bus. In order of priority, these are:

1.

Receive buffer manager write

2.

Receive buffer manager read

3.

Transmit data DMA read

4.

Receive data DMA write

5.

Transmit buffer manager read

6.

Transmit buffer manager write

The FIFO depths are 1

28

bytes for receive and 1

28

bytes for transmit and are a function of the system clock speed,

memory latency and network speed.