Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sen-
sors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit
data bus.

This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The
reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video)
and EAV (end of active video) delimiters in the data stream.

The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and can trigger an
interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is
used, an interrupt can be triggered on each delimiter event.

For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB
5:6:5 and may be processed before the storage in memory. The data stream may be sent on both preview path
and codec path if the bit ISI_CDC in the ISI_CTRL is one. To optimize the bandwidth, the codec path should be
enabled only when a capture is required. 

In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which rep-
resent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the
GS_MODE bit in the ISI_CFG2 register. The codec datapath is not available when grayscale image is selected.

A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.

The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are
shown in 

 and 

In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK),
after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the control register. 

The

 

ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface. 

There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one
at the end of each video data block EAV(0xFF00009D). Only data sent between EAV and SAV is captured. Hori-
zontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the
ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both
frame and line synchronization properly, at least one line of vertical blanking is mandatory. 

HSYNC and VSYNC Synchronization

ISI_VSYNC

ISI_HSYNC

ISI_PCK

 Frame

1 line

Y

Cb

Y

Cr

Y

Cb

Y

Cr

Y

Cb

Y

Cr

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