Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK

 902

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and stored in the

 of the current channel and in the 

The channel EOC bit and the bit DRDY in the 

 are both set. If the PDC channel is

enabled, DRDY rising triggers a data transfer. In any case, either EOC and DRDY can trigger an interrupt.

 registers clears the corresponding EOC bit. 

 clears the DRDY bit and the EOC bit corresponding to the last

converted channel.

EOCx and DRDY Flag Behavior 

.

In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in the

. 

The OVRE and GOVRE flags are automatically cleared when the 

Conversion

Time

Read the ADC_CDRx

EOCx

DRDY

Read the ADC_LCDR

CHx

(ADC_CHSR)

(ADC_SR)

(ADC_SR)

Write the ADC_CR
   with START = 1

Write the ADC_CR
   with START = 1

SHTIM

Conversion

Time

SHTIM