Техническая Спецификация для Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK
![Atmel](https://files.manualsbrain.com/attachments/0369829915bda09f9c2e00fb805a7753579683b5/common/fit/150/50/8d2bf08978ec3e5bc63f4343ac5e91ce8d0e40045619fa520d910d64af8f/brand_logo.png)
Модели
AT91SAM9G25-EK
192
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
22.12.2 Clock Switching Waveforms
Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock
Figure 22-4. Switch Master Clock from Main Clock to Slow Clock
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLL Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR