Техническая Спецификация для Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK

492

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer 
and the new values used for the new buffer. Depending on the row number in 

, some or all of the 

DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their 
initial value at the start of a buffer transfer.

In this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer. 
Enabling the source or destination address to be contiguous between buffers is a function of 
DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.DST_REP, DMAC_CFGx.SRC_REP and DMAC_CTRLAx.DST_DSCR 
registers.

At the end of every buffer transfer, an end of buffer interrupt is asserted if:



The channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number.

Note:

The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destination.

At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:



The channel end of the Chained Buffer Transfer Completed Interrupt is unmasked, DMAC_EBCIMR.CBTCx = ‘1’, 
when n is the channel number.

All multi-buffer transfers must end as shown in Row 1 of 

. At the end of every buffer transfer, the 

DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last 
buffer and the DMAC transfer is terminated. 

For rows 9, 10 and 11 of 

, (DMAC_DSCRx = 0 and DMAC_CTRLBx.AUTO is set), multi-buffer 

DMAC transfers continue until the automatic mode is disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit 
should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer. 
This puts the DMAC into Row 1 state.

For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so 
that LLI.DMAC_DSCRx is set to 0.

Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be 
programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. 
The different transfer types are shown in 

The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, 
and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled.

1.

Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status regis-
ter, DMAC_EBCISR.

3.

Program the following channel registers: