Техническая Спецификация для Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK
Модели
AT91SAM9G25-EK
684
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select
line to remain active (low) during a full set of transfers might lead to communication errors.
line to remain active (low) during a full set of transfers might lead to communication errors.
To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT
bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active)
until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active. To
have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must
be set at 1 before writing the last data to transmit into the SPI_TDR.
bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active)
until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active. To
have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must
be set at 1 before writing the last data to transmit into the SPI_TDR.
35.7.3.9 Peripheral Deselection with DMAC
When the Direct Memory Access Controller is used, the chip select line will remain low during the whole transfer since
the TDRE flag is managed by the DMAC itself. The reloading of the SPI_TDR by the DMAC is done as soon as TDRE
flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other DMAC
channels connected to other peripherals are in use as well, the SPI DMAC might be delayed by another (DMAC with a
higher priority on the bus). Having DMAC buffers in slower memories like flash memory or SDRAM compared to fast
internal SRAM, may lengthen the reload time of the SPI_TDR by the DMAC as well. This means that the SPI_TDR might
not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer
and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed.
the TDRE flag is managed by the DMAC itself. The reloading of the SPI_TDR by the DMAC is done as soon as TDRE
flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other DMAC
channels connected to other peripherals are in use as well, the SPI DMAC might be delayed by another (DMAC with a
higher priority on the bus). Having DMAC buffers in slower memories like flash memory or SDRAM compared to fast
internal SRAM, may lengthen the reload time of the SPI_TDR by the DMAC as well. This means that the SPI_TDR might
not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer
and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed.
shows different peripheral deselection cases and the effect of the CSAAT bit.
Figure 35-10.Peripheral Deselection
A
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
A
DLYBCS
DLYBCT
A
PCS = A
A
A
DLYBCT
A
A
CSAAT = 0
DLYBCT
A
A
CSAAT = 1
A