Техническая Спецификация для Infineon Technologies Hex-Half-Bridge / Double Six-Driver TLE 6208-6 G DEMOBOARD TLE 6208-6G DEMOBOARD TLE 6208-6G
Модели
DEMOBOARD TLE 6208-6G
TLE 6208-6 G
Data Sheet
17
2007-09-12
Data Input Timing
Clock period
t
pCLK
500
–
–
ns
–
Clock high time
t
CLKH
250
–
–
ns
–
Clock low time
t
CLKL
250
–
–
ns
–
Clock low before CSN low
t
bef
250
–
–
ns
–
CSN setup time
t
lead
250
–
–
ns
–
CSN high time
t
CSNH
12
–
–
µs
–
CLK setup time
t
lag
250
–
–
ns
–
Clock low after CSN high
t
beh
250
–
–
ns
–
DI setup time
t
DISU
40
–
–
ns
–
DI hold time
t
DIHO
40
–
–
ns
–
Input signal rise time
at pin DI, CLK and CSN
at pin DI, CLK and CSN
t
rIN
–
–
200
ns
–
Input signal fall time
at pin DI, CLK and CSN
at pin DI, CLK and CSN
t
fIN
–
–
200
ns
–
Data Output Timing
DO rise time
t
rDO
–
50
100
ns
C
L
= 100 pF
DO fall time
t
fDO
–
50
100
ns
C
L
= 100 pF
DO enable time
t
ENDO
–
–
250
ns
low impedance
DO disable time
t
DISDO
–
–
250
ns
high impedance
DO valid time
t
VADO
–
100
250
ns
V
DO
< 0.2
V
CC
;
V
DO
> 0.7
V
CC
;
C
L
= 100 pF
Note: SPI timing ia guaranteed by design. CSN high time: This is the minimum time the
user must wait between SPI commands.
2.3
Electrical Characteristics (cont’d)
8 V <
V
S
< 40 V; 4.75 V <
V
CC
< 5.25 V; INH = High; all outputs open; – 40
°C <
T
j
< 150
°C;
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ.
max.