Техническая Спецификация для Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The following checks are performed:

1.

Century (check if it is in range 19 - 20 or 13-14 in Persian mode)

2.

Year (BCD entry check)

3.

Date (check range 01 - 31)

4.

Month (check if it is in BCD range 01 - 12, check validity regarding “date”)

5.

Day (check range 1 - 7)

6.

Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24-
hour mode; in 12-hour mode check range 01 - 12)

7.

Minute (check BCD and range 00 - 59)

8.

Second (check BCD and range 00 - 59)

Note:

If the 12-hour mode is selected by means of the RTC_MR register, a 12-hour value can be programmed and the 
returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the 
AM/PM indicator (bit 22 of RTC_TIMR register) to determine the range to be checked.

To improve the reliability and security of the RTC, a permanent check is performed on the internal free running counters 
to report non-BCD or invalid date/time values.

An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The flag can 
be cleared by programming the TDERRCLR in the RTC status clear control register (RTC_SCCR). 

Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the TDERR 
flag. The clearing of the source of such error can be done either by reprogramming a correct value on RTC_CALR and/or 
RTC_TIMR registers. 

The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e. every 10 
seconds for SECONDS[3:0] bitfield in RTC_TIMR register). In this case the TDERR is held high until a clear command is 
asserted by TDERRCLR bit in RTC_SCCR register.

To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the 
Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to 
update calendar fields (century, year, month, date, day).

Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it 
is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate 
Time and Calendar register.

Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control 

When entering programming mode of the calendar fields, the time fields remain enabled. When entering the 
programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the 
calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be 
updated before entering programming mode. In successive update operations, the user must wait at least one second 
after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done 
by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, 
the SEC flag must also be cleared.