Техническая Спецификация для Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO
Модели
ATSAMD20-XPRO
406
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.8.1 I
2
C Slave Register Description
26.8.1.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00000000
Property:
Write-Protected, Enable-Protected, Write-Synchronized
z
Bit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 30 – LOWTOUT: SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the slave will release its clock hold, if
enabled, and reset the internal state machine. Any interrupts set at the time of time-out will remain set.
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the slave will release its clock hold, if
enabled, and reset the internal state machine. Any interrupts set at the time of time-out will remain set.
0: Time-out disabled.
1: Time-out enabled.
This bit is not synchronized.
z
Bits 29:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits define the SDA hold time with respect to the negative edge of SCL.
Bit
31
30
29
28
27
26
25
24
LOWTOUT
Access
R
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
SDAHOLD[1:0]
PINOUT
Access
R
R
R/W
R/W
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
MODE[2:0]=100
ENABLE
SWRST
Access
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0