Техническая Спецификация для Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO

Модели

ATSAMD20-XPRO

627

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

- Configure the cache in LOW_POWER mode by writing 0x1 into the NVMCTRL
CTRLB.READMODE bits.

35.3

Revision B

35.3.1 NVMCTRL

1 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the on-
chip flash size minus half a row. Errata reference: 11988

Fix/Workaround:

When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.

35.3.2 VREG

1 - With default bit and register settings the device does not work as
specified in STANDBY mode if load current exceeds 100µA. Errata
reference: 11082

Fix/Workaround:

Set the FORCELDO bit in the VREG register.

35.3.3 Device

1 - The values stored in the NVM software calibration area for the DFLL
calibration are not valid. Errata reference: 12843

Fix/Workaround:

None.

2 - Clock Failure detection for external OSC does not work in standby mode.
Errata reference: 12688

Fix/Workaround:

Before entering standby mode, move the CPU clock to an internal RC, disable
external OSC and disable the Clock Failure detector. Upon CPU wakeup, restart
external OSC (if it does not start, the failure occurred during standby), enable the
Clock Failure detector and move the CPU clock to the external OSC.

3 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416

Fix/Workaround: