Техническая Спецификация для Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD
Модели
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
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When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor
has not written a fault address to SCB_MMFAR.
• MLSPERR: MemManage during Lazy State Preservation
This is part of
.
0: No MemManage fault occurred during the floating-point lazy state preservation.
1: A MemManage fault occurred during the floating-point lazy state preservation.
1: A MemManage fault occurred during the floating-point lazy state preservation.
• MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag
This is part of
.
0: The value in SCB_MMFAR is not a valid fault address.
1: SCB_MMFAR holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
1: SCB_MMFAR holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose SCB_MMFAR
value has been overwritten.
• IBUSERR: Instruction Bus Error
This is part of
.
0: No instruction bus error.
1: Instruction bus error.
The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it
1: Instruction bus error.
The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it
attempts to issue the faulting instruction.
When the processor sets this bit to 1, it does not write a fault address to the BFAR.
When the processor sets this bit to 1, it does not write a fault address to the BFAR.
• PRECISERR: Precise Data Bus Error
This is part of
.
0: No precise data bus error.
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused
the fault.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR.
• IMPRECISERR: Imprecise Data Bus Error
This is part of
.
0: No imprecise data bus error.
1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the
1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the
error.
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR.
This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR.
This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault
priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority pro-
cesses. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects
that both this bit and one of the precise fault status bits are set to 1.
• UNSTKERR: Bus Fault on Unstacking for a Return From Exception
This is part of
.
0: No unstacking fault.