Техническая Спецификация для Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD
Модели
ATSAM4S-WPIR-RD
265
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
Little-endian (LE)
Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing
,
Little-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
See also
See also
.
Load/store architecture
A processor architecture where data-processing operations only operate on register contents, not
directly on memory contents.
Memory Protection Unit
(MPU)
Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
Prefetching
In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before
the preceding instructions have finished executing. Prefetching an instruction does not mean that the
instruction has to be executed.
Preserved
Preserved by writing the same value back that has been previously read from the same field on the
same processor.
Read
Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb
instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Region
A partition of memory space.
Reserved
A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These fields
are reserved for use in future extensions of the architecture or are implementation-specific. All
reserved bits not used by the implementation must be written as 0 and read as 0.
Thread-safe
In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing
shared resources, to ensure correct operation without the risk of shared access conflicts.
Thumb instruction
One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be
halfword-aligned.