Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
132
AT32UC3A
19. HSB Bus Matrix (HMATRIX)
Rev: 2.3.0.1
19.1
Features
•
User Interface on peripheral bus
•
Configurable Number of Masters (Up to sixteen)
•
Configurable Number of Slaves (Up to sixteen)
•
One Decoder for Each Master
•
Three Different Memory Mappings for Each Master (Internal and External boot, Remap)
•
One Remap Function for Each Master
•
Programmable Arbitration for Each Slave
– Round-Robin
– Fixed Priority
•
Programmable Default Master for Each Slave
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
•
One Cycle Latency for the First Access of a Burst
•
Zero Cycle Latency for Default Master
•
One Special Function Register for Each Slave (Not dedicated)
19.2
Description
The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
19.3
Memory Mapping
The Bus Matrix provides one decoder for every HSB Master Interface. The decoder offers each
HSB Master several memory mappings. In fact, depending on the product, each memory area
may be assigned to several slaves. Booting at the same address while using different HSB
slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MRCR) that performs
The Bus Matrix user interface provides Master Remap Control Register (MRCR) that performs
remap action for every master independently.
19.4
Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master and fixed default master.
32058K
AVR32-01/12