Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
147
AT32UC3A
20.4
I/O Lines Description
Depending on the Memory Controller in use, all signals are not connected directly through the
Mux Logic.
details the connections between the two Memory Controllers and the
EBI pins.
Table 20-1.
EBI I/O Lines Description
Name
Function
Type
Active Level
EBI
D0 - D15
Data Bus
I/O
A0 - A23
Address Bus
Output
NWAIT
External Wait Signal
Input
Low
SMC
NCS0 - NCS3
Chip Select Lines
Output
Low
NWR0 - NWR3
Write Signals
Output
Low
NOE
Output Enable
Output
Low
NRD
Read Signal
Output
Low
NWE
Write Enable
Output
Low
NBS0 - NBS3
Byte Mask Signals
Output
Low
SDRAM Controller
SDCK
SDRAM Clock
Output
SDCKE
SDRAM Clock Enable
Output
High
BA0 - BA1
Bank Select
Output
SDWE
SDRAM Write Enable
Output
Low
RAS - CAS
Row and Column Signal
Output
Low
NWR0 - NWR3
Write Signals
Output
Low
NBS0 - NBS3
Byte Mask Signals
Output
Low
SDA10
SDRAM Address 10 Line
Output
Table 20-2.
EBI Pins and Memory Controllers I/O Lines Connections
EBI Pins
SDRAMC I/O Lines
SMC I/O Lines
NWR1/NBS1
NBS1
NWR1/NUB
A0/NBS0
Not Supported
SMC_A0/NLB
A1/NBS2/NWR2
Not Supported
SMC_A1
A[11:2]
SDRAMC_A[9:0]
SMC_A[11:2]
SDA10
SDRAMC_A10
Not Supported
A12
Not Supported
SMC_A12
A[14:13]
SDRAMC_A[12:11]
SMC_A[14:13]
32058K
AVR32-01/12