Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
486
AT32UC3A
29.7.28
MACB Statistic Registers
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read
frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit
is set in the network control register. To write to these registers, bit 7, WESTAT, in the network control register, NCR, must
be set. The statistics register block contains the following registers.
29.7.28.1
Pause Frames Received Register
Register Name:
PFR
Access Type:
Read/Write
• FROK: Pause Frames received OK
A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit
8, BIG, in network configuration register, NCFGR, is set, 10240 if bit 3, JFRAME in network configuration register, NCFGR,
is set) and has no FCS, alignment or receive symbol errors.
29.7.28.2
Frames Transmitted OK Register
Register Name:
FTO
Access Type:
Read/Write
• FTOK: Frames Transmitted OK
A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
FROK
7
6
5
4
3
2
1
0
FROK
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
FTOK
15
14
13
12
11
10
9
8
FTOK
7
6
5
4
3
2
1
0
FTOK
32058K
AVR32-01/12