Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
499
AT32UC3A
30.3
Block Diagram
The USB controller provides a hardware device to interface a USB link to a data flow stored in a
dual-port RAM (DPRAM).
The USB controller requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock
The USB controller requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock
generated from one of the power manager oscillators, optionally through one of the power man-
ager PLLs.
The 48 MHz clock is used to generate a 12 MHz full-speed (or 1.5 MHz low-speed) bit clock from
The 48 MHz clock is used to generate a 12 MHz full-speed (or 1.5 MHz low-speed) bit clock from
the received USB differential data and to transmit data according to full- or low-speed USB
device tolerance. Clock recovery is achieved by a digital phase-locked loop (a DPLL, not repre-
sented), which complies with the USB jitter specifications.
Figure 30-1.
Block Diagram
Interrupt
Controller
USB Interrupts
D-
VBUS
USB_VBOF
USB
GPIO
Controller
USB_ID
D+
User Interface
Power
Manager
USB GCLK @ 48 MHz
PB
DPRAM
USB 2.0
Core
PEP
Allocation
DMA
HSB MUX
Local
HSB
Slave Interface
HSB1
HSB0
Master
Slave
Domain
USB Clock
System Clock
Domain
32 bits
HSB
32058K
AVR32-01/12