Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
509
AT32UC3A
30.7.1.8
Customizing of OTG Timers
It is possible to refine some OTG timers thanks to the TIMPAGE and TIMVALUE bit-fields, as
shown by
TIMPAGE is used to select the OTG timer to access while TIMVALUE indicates the time-out
value of the selected timer.
TIMPAGE and TIMVALUE can be read or written. Before writing them, the firmware should
TIMPAGE and TIMVALUE can be read or written. Before writing them, the firmware should
unlock write accesses by setting the UNLOCK bit. This is not required for read accesses, except
before accessing TIMPAGE if it has to be written in order to read the TIMVALUE bit-field of
another OTG timer.
30.7.1.9
Plug-In Detection
The USB connection is detected from the VBUS pad.
shows the architecture of the
plug-in detector.
Figure 30-11.
Plug-In Detection Input Block Diagram
The control logic of the VBUS pad outputs two signals:
•the Session_valid signal is high when the voltage on the VBUS pad is higher than or equal to
1.4 V;
•the Va_Vbus_valid signal is high when the voltage on the VBUS pad is higher than or equal to
4.4 V.
In device mode, the VBUS bit follows the Session_valid comparator output:
•it is set when the voltage on the VBUS pad is higher than or equal to 1.4 V;
Table 30-4.
Customizing of OTG Timers
TIMPAGE
00b:
AWaitVrise Time-Out
([OTG] Chapter 6.6.5.1)
01b:
VbBusPulsing Time-Out
([OTG] Chapter 5.3.4)
10b:
PdTmOutCnt Time-Out
([OTG] Chapter 5.3.2)
11b:
SRPDetTmOut Time-Out
([OTG] Chapter 5.3.3)
TIM
V
ALUE
00b
20 ms
15 ms
93 ms
10 µs
01b
50 ms
23 ms
105 ms
100 µs
10b
70 ms
31 ms
118 ms
1 ms
11b
100 ms
40 ms
131 ms
11 ms
VBUSTI
USBSTA
VBUS
VBUS
USBSTA
GND
VDD
Pad Logic
Logic
Session_valid
Va_Vbus_valid
R
PU
R
PD
VBus_pulsing
VBus_discharge
32058K
AVR32-01/12