Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
528
AT32UC3A
30.7.3.13
Interrupts
See the structure of the USB host interrupt system on
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).
30.7.3.13.1
Global Interrupts
The processing host global interrupts are:
•the Device Connection interrupt (DCONNI);
•the Device Disconnection interrupt (DDISCI);
•the USB Reset Sent interrupt (RSTI);
•the Downstream Resume Sent interrupt (RSMEDI);
•the Upstream Resume Received interrupt (RXRSMI);
•the Host Start of Frame interrupt (HSOFI);
•the Host Wake-Up interrupt (HWUPI);
•the Pipe X interrupt (PXINT);
•the DMA Channel X interrupt (DMAXINT).
•the Device Disconnection interrupt (DDISCI);
•the USB Reset Sent interrupt (RSTI);
•the Downstream Resume Sent interrupt (RSMEDI);
•the Upstream Resume Received interrupt (RXRSMI);
•the Host Start of Frame interrupt (HSOFI);
•the Host Wake-Up interrupt (HWUPI);
•the Pipe X interrupt (PXINT);
•the DMA Channel X interrupt (DMAXINT).
There is no exception host global interrupt.
30.7.3.13.2
Pipe Interrupts
The processing host pipe interrupts are:
•the Received IN Data interrupt (RXINI);
•the Transmitted OUT Data interrupt (TXOUTI);
•the Transmitted SETUP interrupt (TXSTPI);
•the Short Packet interrupt (SHORTPACKETI);
•the Number of Busy Banks interrupt (NBUSYBK).
•the Transmitted OUT Data interrupt (TXOUTI);
•the Transmitted SETUP interrupt (TXSTPI);
•the Short Packet interrupt (SHORTPACKETI);
•the Number of Busy Banks interrupt (NBUSYBK).
The exception host pipe interrupts are:
•the Underflow interrupt (UNDERFI);
•the Pipe Error interrupt (PERRI);
•the NAKed interrupt (NAKEDI);
•the Overflow interrupt (OVERFI);
•the Received STALLed interrupt (RXSTALLDI);
•the CRC Error interrupt (CRCERRI).
•the Pipe Error interrupt (PERRI);
•the NAKed interrupt (NAKEDI);
•the Overflow interrupt (OVERFI);
•the Received STALLed interrupt (RXSTALLDI);
•the CRC Error interrupt (CRCERRI).
30.7.3.13.3
DMA Interrupts
The processing host DMA interrupts are:
•the End of USB Transfer Status interrupt (EOT_STA);
•the End of Channel Buffer Status interrupt (EOCH_BUFF_STA);
•the Descriptor Loaded Status interrupt (DESC_LD_STA).
•the End of Channel Buffer Status interrupt (EOCH_BUFF_STA);
•the Descriptor Loaded Status interrupt (DESC_LD_STA).
There is no exception host DMA interrupt.
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AVR32-01/12