Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
592
AT32UC3A
30.8.2.18
USB Device DMA Channel X HSB Address Register (UDDMAX_ADDR)
Offset:
0x0314 + (X - 1) . 0x10
Register Name:
UDDMAX_ADDR
, X in [1..6]
Access Type:
Read/Write
Reset Value:
0x00000000
• HSB_ADDR: HSB Address
This field determines the HSB bus current address of a channel transfer.
The address set on the HSB address bus is HSB_ADDR rounded down to the nearest word-aligned address, i.e.
The address set on the HSB address bus is HSB_ADDR rounded down to the nearest word-aligned address, i.e.
HSB_ADDR[1:0] is considered as 00b since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The software may write this field only when the Channel Enabled bit (CH_EN) of the UDDMAX_STATUS register is clear.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB
Channel HSB start and end addresses may be aligned on any byte boundary.
The software may write this field only when the Channel Enabled bit (CH_EN) of the UDDMAX_STATUS register is clear.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB
access byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word
boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel
The packet start address is either the channel start address or the next channel address to be accessed in the channel
buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either
determined by the end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFF_CLOSE_IN_EN) is
set.
31
30
29
28
27
26
25
24
HSB_ADDR
rwu
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
HSB_ADDR
rwu
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
HSB_ADDR
rwu
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HSB_ADDR
rwu
0
0
0
0
0
0
0
0
32058K
AVR32-01/12