Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
794
AT32UC3A
3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and
NCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
Fix/workaround
When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if
CPOL=1 and CPHA=0.
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
Fix/workaround
When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if
CPOL=1 and CPHA=0.
4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first
transfer
In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or
during the first transfer.
In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or
during the first transfer.
Fix/Workaround
1. Set slave mode, set required CPOL/CPHA.
2. Enable SPI.
3. Set the polarity CPOL of the line in the opposite value of the required one.
4. Set the polarity CPOL to the required one.
5. Read the RXHOLDING register.
Transfers can now befin and RXREADY will now behave as expected.
1. Set slave mode, set required CPOL/CPHA.
2. Enable SPI.
3. Set the polarity CPOL of the line in the opposite value of the required one.
4. Set the polarity CPOL to the required one.
5. Read the RXHOLDING register.
Transfers can now befin and RXREADY will now behave as expected.
5. SPI Disable does not work in Slave mode
Fix/workaround
Read the last received data then perform a Software reset.
Read the last received data then perform a Software reset.
41.1.4
Power Manager
1. If the BOD level is higher than VDDCORE, the part is constantly under reset
If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will
be in constant reset.
be in constant reset.
Fix/Workaround
Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than
VDDCORE max and disable the BOD.
Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than
VDDCORE max and disable the BOD.
41.1.5
PDCA
1. Wrong PDCA behavior when using two PDCA channels with the same PID.
Fix/Workaround
The same PID should not be assigned to more than one channel.
The same PID should not be assigned to more than one channel.
41.1.6
TWI
1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
After a Software Reset, the register TWI RHR must be read.
41.1.7
USART
1. ISO7816 info register US_NER cannot be read
The NER register always returns zero.
Fix/Workaround
None
Fix/Workaround
None
41.1.8
Processor and Architecture
1. LDM instruction with PC in the register list and without ++ increments Rp
32058K
AVR32-01/12