Техническая Спецификация для Linear Technology LTC4366-1 Demoboard, Very High Voltage Surge Stopper with Latchoff DC1850A-A DC1850A-A

Модели

DC1850A-A

LTC4366-1/LTC4366-2

436612fd

For more information

www.linear.com/LTC4366

applicaTions inForMaTion

The typical LTC4366 application is a protected system

that distributes power to loads safe from overvoltage

transients. External component selection is discussed in

the following sections.

Dual Shunt Regulators
The LTC4366 uses two shunt regulators coupled with

the external voltage dropping resistors, R

and R

, to

generate internal supply rails at the V

and OUT pins.

These shunt-regulated rails allow overvoltage protection

from unlimited high voltage transients irrespective of the

voltage rating of the LTC4366’s internal circuitry.
At the beginning of start-up, during shutdown, or after an

overvoltage fault, the GATE pin is clamped to the OUT pin

thereby shutting off the MOSFET. This allows the V

and

OUT pins to be pulled to ground by output load and R

Under this condition the V

pin is clamped with a 12V

shunt regulator to V

. The full supply voltage minus 12V

is then impressed on the R

resistor which sets the shunt

current. The shunt current can be as high as 10mA which

is several orders of magnitude higher than the typical 9µA

pin quiescent current.

In normal operation the OUT voltage is equal to the input

supply. With C1 fully charged I

is zero at this point. Under

this condition the voltage between the OUT and V

pins

are clamped with a 5.7V shunt regulator. The input supply

voltage minus 5.7V is impressed on R

. The R

current

is divided into three areas: the 5.7V shunt current, bias

current between OUT and V

and finally the R

current.

The 5.7V shunt current can be as high as 10mA which

greatly exceeds the typical OUT (160µA) bias current.

Turn-On Sequence
The voltage between the V

and V

pins is shunt regu-

lated to 12V after ramping up the input supply. Next, the

internally generated supply, V

, produces a 30µs power-

on-reset pulse which clears the fault latch and initializes

internal latches. Next, the shutdown comparator determines

if the SD pin is externally pulled low, thereby requesting a

low bias current shutdown state. Otherwise the external

MOSFET, M1, is allowed to turn on.
Turning on the 7.5µA GATE pull-up current source from the

pin begins what can be described as a “bootstrapped”

method for powering up the MOSFET gate. Once the GATE

reaches the V

pin voltage (minus a Schottky diode), the

7.5µA source loses voltage headroom and stops charging

the GATE (middle of waveforms in Figure 2.). The bootstrap

method relies on charging C1 to a sufficient voltage after

GATE stops increasing. The voltage on C1 is then used as

a supply for a charge pump that charges the gate to its

final value 12V above OUT. C1 will discharge if the charge

pump current exceeds the C1 charging current. If the

voltage drops below 4.35V, the charge pump will pause

allowing C1 to recharge.

470k

100k

OUT

10nF

GATE

FQA62N25C

10nF

0.47µF

FB1

12.4k

OUT

1.5A

(43V CLAMP)

28V

(18V DC TO 250V DC)

FB2

422k

436612 F01

46.4k

10Ω

324k

MMBT3904

LTC4366-2

TIMER

BASE

Figure 1. Typical Application

Figure 2. Turn-On Waveforms

GATE

10V/DIV

OUT

10V/DIV

5V/DIV

20ms/DIV

436612 TA01b

CHARGE

PUMP PAUSE

CHARGE

PUMP STARTS

C1 CHARGING

C1 RECHARGING