Техническая Спецификация для Linear Technology LTC2471 - Selectable 208sps/833sps, 16-Bit I2C Delta Sigma ADCs with 10ppm/C Max Precision Reference (Req DC590B) Linear DC1718A
Модели
DC1718A
LTC2471/LTC2473
7
24713fb
applicaTions inForMaTion
CONVERTER OPERATION
Converter Operation Cycle
The LTC2471/LTC2473 are low power, delta sigma, analog
The LTC2471/LTC2473 are low power, delta sigma, analog
to digital converters with a simple I
2
C interface and a user
selected 208sps/833sps output rate (see Figure 1). The
LTC2473 has a fully differential input while the LTC2471 is
single-ended. Both are pin and software compatible. Their
operation is composed of three distinct states: CONVERT,
SLEEP/NAP, and DATA INPUT/OUTPUT. The operation
begins with the CONVERT state (see Figure 2). Once the
conversion is finished, the converter automatically pow-
ers down (NAP) or under user control, both the converter
and reference are powered down (SLEEP). The conversion
result is held in a static register while the device is in this
state. The cycle concludes with the DATA INPUT/OUTPUT
state. Once all 16-bits are read or an abort is initiated, the
device begins a new conversion.
The CONVERT state duration is determined by the LTC2471/
The CONVERT state duration is determined by the LTC2471/
LTC2473 conversion time (nominally 4.8ms or 1.2ms
depending on the selected output rate). Once started,
this operation can not be aborted except by a low power
supply condition (V
CC
< 2.1V) which generates an internal
power-on reset signal.
Figure 2. LTC2471/LTC2473 State Transition Diagram
DATA INPUT/OUTPUT
SLEEP/NAP
CONVERT
POWER-ON RESET
YES
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F02
STOP
OR
READ 16 BITS
READ/WRITE
ACKNOWLEDGE
NO
YES
NO
block DiagraM
Figure 1. Functional Block Diagram
ΔΣ A/D
CONVERTER
DECIMATING
SINC FILTER
SDA
REFOUT
COMP
REF
–
IN
+
(IN)
IN
–
(GND)
SCL
A
O
24713 BD
–
ΔΣ A/D
CONVERTER
INTERNAL
REFERENCE
( ) PARENTHESIS INDICATE LTC2471
SPI
INTERFACE
INTERNAL
OSCILLATOR
1
V
CC
12
2
3
5
6
8
GND
4, 7, 11, 13 DD PACKAGE
4, 7, 11 MS PACKAGE
9
10